公司名稱

TSMC Design Tech. Japan, Inc.

工作地點

日本-橫濱市

職務張貼日

2022/05/18

Job Description

1. RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
2. Design flow/methodology development and innovation for front-end design challenges.
3. Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.

 

■Qualification
1. BCH and above in EE, CS related fields.
2. 3-10 years working experience. Especially, experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification.
3. Familiar with EDA CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
4. Familiar with tcl/Perl/Python/C++ program.
5. PPA improvement experience is a plus.
6. Familiar with CPU architecture is a plus.
7. Good command of Japanese. Fluent in English is a plus."

TSMC 企業核心價值

台積公司誠摯招募志同道合的夥伴，與我們一同驅動企業邁向成功。我們深信，核心價值是我們企業文化的基石。因此，應徵者必須認同核心價值，並積極地落實在工作中。 

• 誠信正直： 說真話、不誇張、不作秀。一旦答應，必定不計代價，全力以赴。
• 承諾： 同仁全心全意投入公司，抱著「公司成功、我也成功」的心情，熱忱認真地工作，並且做出最大貢獻。因為承諾是雙向的，公司也會為照顧員工權益全力以赴。 
• 創新：創新是公司成長的泉源，不僅僅是有新的想法，還要執行力，做出改變。 
• 客戶信任： 我們努力與客戶建立深遠的夥伴關係，並成為客戶信賴且賴以成功的長期重要夥伴。

 ( TSMC 核心價值詳細資訊請參考：https://www.tsmc.com/chinese/aboutTSMC/values)