Job Description

1. RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
2. Design flow/methodology development and innovation for front-end design challenges.
3. Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.

■Qualification
1. BCH and above in EE, CS related fields.
2. 3-10 years working experience. Especially, experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification.
3. Familiar with EDA CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
4. Familiar with tcl/Perl/Python/C++ program.
5. PPA improvement experience is a plus.
6. Familiar with CPU architecture is a plus.
7. Good command of Japanese. Fluent in English is a plus."