公司名稱

歐洲子公司

工作地點

德國-慕尼黑

專業領域

研究發展

職別

工程師/管理師

職務類型

正職

職務張貼日

2026/07/02

Taiwan Semiconductor Manufacturing Company Ltd. (“TSMC”) is the world’s leading semiconductor foundry. Headquartered in Taiwan, the Company has operation facilities worldwide and the largest logic chip manufacturing capacity in global semiconductor industry. The Company employs a global workforce of over 89.000 and recorded revenue over US$122 billion in 2025. TSMC produces the chips that are found in smart phones, tablets, computers, smart TVs, cars, laptops, games consoles, data centers and many more applications. TSMC sells to a wide variety of customers, including most leading semiconductor companies.

At the TSMC EU Design Center, you’ll work in an exceptional technology and design team to refine your technical and leadership skills within the world's most advanced design service ecosystem. You'll be contributing to the forefront of semiconductor technology, including cutting-edge nonvolatile memory solutions like MRAM and RRAM. Your main focus will be to assist our leading customers in delivering state-of-the-art products that have a transformative impact on people's lives.

職務說明

• DFT Architecture & Leadership: Define, architect, and document the complete DFT strategy for complex SoC. Lead and mentor a team of DFT engineers throughout the project lifecycle.

• Flow Development: Design, implement, and maintain DFT flows utilizing Synopsys (DFTMAX, TetraMAX, PrimeShield) and Siemens Tessent (Tessent Shell, TestKompress) toolsets.

• iJTAG Integration: Serve as the internal expert on iJTAG (IEEE 1687). Architect and implement hierarchical iJTAG networks, instrument connectivity, and ICL/PDL description generation for IP block integration.

• Implementation: Drive the insertion of Scan, MBIST (Memory Built-In Self-Test), LBIST, and Analog Macro test structures.

• ATPG & Verification: Generate and validate high-quality ATPG patterns (stuck-at, transition fault, path delay, and cell-aware). Perform extensive pre-silicon DFT verification at both block and full-chip levels using gate-level simulations (GLS) with timing.

• Physical Design Collaboration: Work closely with the Synthesis and Physical Design teams to resolve DFT-related timing closure, routing congestion, and power issues.

• Silicon Bring-up & Diagnostics: Lead post-silicon validation, ATE (Automatic Test Equipment) deployment, and debug activities to diagnose yield issues and silicon failures.

職務要求

• Master's degree or above in Electrical Engineering or any other related majors.

• Over 5 years of experience of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs.

• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST.

• Experience with Synopsys DFT Complier, Tetramax and VCS is required. Experience with Tessent and Modus/Encounter tool suite is a plus.

• Strong programming skills in Python/TCL and shell scripting is required.

TSMC 企業核心價值

台積公司誠摯招募志同道合的夥伴，與我們一同驅動企業邁向成功。我們深信，核心價值是我們企業文化的基石。因此，應徵者必須認同核心價值，並積極地落實在工作中。 

• 誠信正直： 說真話、不誇張、不作秀。一旦答應，必定不計代價，全力以赴。
• 承諾： 同仁全心全意投入公司，抱著「公司成功、我也成功」的心情，熱忱認真地工作，並且做出最大貢獻。因為承諾是雙向的，公司也會為照顧員工權益全力以赴。 
• 創新：創新是公司成長的泉源，不僅僅是有新的想法，還要執行力，做出改變。 
• 客戶信任： 我們努力與客戶建立深遠的夥伴關係，並成為客戶信賴且賴以成功的長期重要夥伴。

 ( TSMC 核心價值詳細資訊請參考：https://www.tsmc.com/chinese/aboutTSMC/values)

It is the policy of TSMC EU to provide equal employment opportunity (EEO) to all persons regardless of age, color, ethnic and national origin, citizenship status, physical or mental disability, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, genetic information, marital status, status with regard to public assistance, veteran status, or any other characteristic protected by federal, state or local law.