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会社
台湾積体電路製造股份有限公司
会社所在地
台湾
職種
ICデザイン技術
職種
エンジニア/管理者
雇用形態
正社員
投稿日
2026/03/17
Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of over 17 million 12-inch equivalent wafers in 2025. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.
In R&D, Design and Technology Platform (DTP) provides differentiated and world-leading design solutions to enable the implementation of System on Chip (SoC) for leading AI/HPC, communication, automotive and IoT applications on TSMC's diverse silicon and packaging technology platform. We work with the world's leading SoC design teams and ecosystem experts to promote industry-leading process design kits (PDKs) and reusable design blocks for the semiconductor intellectual property core (IP), including standard cell libraries, embedded memory, general-purpose input/output (GPIO), simulation and interface IP, as well as electronic design automation (EDA) tools and design flows for monolithic SoCs and heterogeneous 3DICs. This allows us to accelerate the process of transforming innovation into silicon chips and creating revolutionary changes in daily life!
職務内容
Introduction to our division, System and Chip Design Solutions Development Division.
 
We are digital implementation team inside TSMC. Our mission is to integrate latest process technology with most updated commercial design content (CPU, GPU, DSP, etc.) to demonstrate expected performance, power, and area (PPA) improvement. Our results and developed flows are references for worldwide 1st tier design houses.

Job scope covered by our division:

1. Technology related benchmark & design methodology development.

To understand PPA of TSMC’s new technology and explore possible applications, benchmark activities are conducted. And upon results, technology refinement opportunity to achieve “Design-Technology Co-Design” (DTCO) concept would be explored and tested. Through these benchmark activities, we are also in charge of developing design methodology needed for new process technology.

2. System design & yield learning.

Our division has the only system design team in TSMC. System-level architectures of all test chips in TSMC are developed and defined by our division. Additionally, we have dedicated team for “design-for-test” and “design-for-diagnosis” methodology. This is to ensure defects of test chips can be well detected, located, and analyzed. Related results are critical for yield learning and enhancement for TSMC.

3. Test chip implementation & flow issue solving.

To have design flow (from RTL to GDS) for latest technology truly verified and pipe-cleaned based on product-like design content and spec., real test chip implementation is needed for TSMC. This is also critical for yield learning and improvement. Implementation of such test chip is one of division’s major charter. Comparing to other test chip implementation teams in TSMC, test chips owned by us is most “product-like”. This is to trigger issues that are design and spec. dependent. During implementation stages, we need to analyze and solve these issues so that when customers are using related technology, solutions are well prepared.

4. Support to 1st-tier customers for adopting TSMC’s advanced technology.

When customers are adopting TSMS’s new technologies, they would encounter technical issues not experienced before. Support from TSMC is highly expected to ensure on-schedule project execution. In TSMC, our division is the only team that have experience on integrating latest technology and product-level design content. Thus, we are responsible for providing such services in forms of technical consultant, on-site case debugging, or utility development.

Organization of our division & recruiting departments:

1. Our division, SCDSD, is under Design and Technology Platform (DTP). SCDSD currently have ~150 members distributed in offices at Hsinchu (Taiwan), San Jose (U. S.), and Nanjing (China). Yokohama office is now under planning. Our division work like a mini design house covering all design stages from systemlevel definition to GDS tape-out. Thus, all design stages for digital implementation are covered. (ex: system design, RTL coding, synthesis, DFT, MBIST, verification, PG network design, floorplan, place, CTS, route, timing analysis, power analysis, physical verification, CAD support, etc.)

2.For this job position, we are recruiting talents for below three departments on Hsinchu site. Below are brief introductions to job scopes of these three departments.

Test Chip Development Department:

1. FE implementation and related flow development, covering stages of system-level design, RTL coding, verification, DFT, MBIST, and synthesis.
2. Architecture & methodology development for “design-for-test (DFT)” and “design-for-diagnosis”, focusing on yield learning purpose.
3. Architecture & methodology development for silicon correlation.

Test Chip Physical Design Department:

1. BE implementation and related flow development, covering stages of chip-level planning, PG network design, floorplan, place, CTS, route, power analysis (PDNA sign-off), and physical verification.
2. Design methodology and related CAD utility development for BE implementation, especially for solving issues triggered by new technology. Additionally, we also develop utilities for customer support purpose.
3. Technology benchmark to understand PPA of new technologies.

Chip Implementation CAD:

1. Flow development for RC extraction, timing analysis, and timing fixing
2. CAD platform development for design stage integration, design kits management, and design DB management
3. CAD/EDA development in general for solving all kinds of design issues
職務資格
Expected expertise or technical skills expected:
 
1. Digital implementation concept in general. Familiar w/i. at least one of below design stages for digital implementation.
2. System design, RTL coding, synthesis, DFT, MBIST, verification, PG network design, floorplan, place, CTS, route, timing analysis, power analysis, and physical verification.
3. Linux operation capability.

Scripting and/or programming skill:

1. Knowledge to EDArelated algorithm is nice to have but not necessary.


#LI-DNI
TSMC 価値観
TSMCは、私たちのビジョンと価値観に共感していただき、会社の持続的な成功に貢献していただける仲間を募集しています。私たちのコアバリューは、企業文化を形成する礎であり、すべての決断や行動の指針であります。以下のプリンシプルに心が響き、業務に体現していただける応募者を心よりお待ちしています。 
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  • コミットメント:コミットメントは社員と会社の間に存在する双方向性です。社員は会社に対してロイヤリティを持ち、会社の成功は自分の成功であると心構え、勤勉に働いてベストを尽くします。一方で、会社は社員の利益を最大限に考慮するよう尽力します。 
  • イノベーション: イノベーションは会社成長の源泉です。新しいアイデアを発想することに留まらず、そのアイデアを実践するこそがイノベーションです。 
  • お客様の信頼:私たちは、お客様と深く永続的なパートナーシップを築くことに尽力します。長期にわたり、お客様の成功を支える、頼れるパートナーであり続けます。
 (TSMCのコアバリューに関する詳細は、こちらをご参照ください:https://www.tsmc.com/japanese/aboutTSMC/values)
Fostering a global inclusive workplace reflects TSMC’s core values and business philosophy and is essential for our future success. Our commitment to global inclusive workplace allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. We strive to create a workplace that is equitable and accessible to all employees. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.