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Company
Taiwan Semiconductor Manufacturing Company Limited
Location
Taiwan
Career Area
IC Design Technology
Job Type
Engineer / Admin
Employment Type
Regular
Posted
Feb 20, 2023
Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.

In R&D, Design and Technology Platform (DTP) provides differentiated and world-leading design solutions to enable the implementation of System on Chip (SoC) for leading AI/HPC, communication, automotive and IoT applications on TSMC's diverse silicon and packaging technology platform. We work with the world's leading SoC design teams and ecosystem experts to promote industry-leading process design kits (PDKs) and reusable design blocks for the semiconductor intellectual property core (IP), including standard cell libraries, embedded memory, general-purpose input/output (GPIO), simulation and interface IP, as well as electronic design automation (EDA) tools and design flows for monolithic SoCs and heterogeneous 3DICs. This allows us to accelerate the process of transforming innovation into silicon chips and creating revolutionary changes in daily life!
Job Responsibilities
Organization Introduction:
 
We are power grid design and sign-off team for digital design inside TSMC. The mission is to develop power grid design and co-optimize with semiconductor process in advanced technology nodes for most updated commercial design contents (CPU, GPU, SoC, etc.).
Our power grid designs are references for worldwide 1st Tier design houses.

 Responsibilities:

1.Develop power grid structure for most updated commercial design contents (CPU, GPU, SoC, etc.) and check IR/EM (Electron-Migration) performance
2.Provide design solutions for IR/EM and routing optimization
3.Co-work with process R&D for process tuning to achieve better PDN (Power Delivery Network) design
4.Support TSMC advanced process node test chip PDN sign-off checks, including PDN quality check, static/dynamic IR sign-off, and EM sign-off for successful chip tape-out
5.Provide guidance and suggestion to PnR (Place and Route) designer on PDN issue fixing
Job Qualifications
1. Master of Science in Electrical Engineering is required
2. Knowledge of Electronics, Circuitry, and Semiconductor Physics/Devices for PDN structure design and IR results analysis is required
3. Basic programming skills, such as Perl, Python, C++ for flow automation, data analysis, and results summary are required
4. Better to have digital design PnR experience from floorplan stage, placement, CTS (Clock Tree Synthesis) to routing stage
5. Being familiar with digital design PnR flow is preferred
6. Being familiar with SPICE (Simulation Program with Integrated Circuit Emphasis) and mixed-mode simulation is a plus
7. Fluent English in speaking and in writing