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公司名稱
台灣積體電路製造股份有限公司
工作地點
台灣
專業領域
IC 設計技術
職別
工程師/管理師
職務類型
正職
職務張貼日
2023/08/03
Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.

In R&D, Design and Technology Platform (DTP) provides differentiated and world-leading design solutions to enable the implementation of System on Chip (SoC) for leading AI/HPC, communication, automotive and IoT applications on TSMC's diverse silicon and packaging technology platform. We work with the world's leading SoC design teams and ecosystem experts to promote industry-leading process design kits (PDKs) and reusable design blocks for the semiconductor intellectual property core (IP), including standard cell libraries, embedded memory, general-purpose input/output (GPIO), simulation and interface IP, as well as electronic design automation (EDA) tools and design flows for monolithic SoCs and heterogeneous 3DICs. This allows us to accelerate the process of transforming innovation into silicon chips and creating revolutionary changes in daily life!
職務說明
Job content:
 
1. Hands on SOC chip/ block implementation from gate level netlist to GDS tape-out.
2. Develop IC design methodology.
3. Chip tape-out; Design methodology development.
職務要求
Requirement:
 
1. Experience in tape-out with multi-million gates count SOC design. 16nm/10nm/7nm design experience is a plus.
2. Solid skillsets of Cadence/Synsopsys/Mentor EDA tools.
3. Capable of executing timing budgeting, synthesis, P&R, CTS, timing closure, DFT, physical verification, DFM and spice simulations.
4. Experience in CAD methodology and problem solving skill.
5. Familiar with Verilog, Perl/Tcl and C/C++.
6. Good communication in English.
7. Master Degree or above.

Diversity, Equity and Inclusion (DE&I) reflects TSMC’s core values and business philosophy and is essential for our future success. Our commitment to DE&I allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. To strive to create a workplace that is equitable and accessible to all employees, we also provide reasonable accommodations for qualified individuals with disabilities. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.