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公司名稱
TSMC Design Technology Japan, Inc.
工作地點
日本-橫濱市
職務類型
約聘
職務張貼日
2022/05/18

Job Description

• Verify TSMC’s product like ARM processor based SOC and memory subsystem test chips
• Develop verification methodology and implement test bench components using System Verilog, UVM, and low power verification
• Develop comprehensive test plan and implement test cases to verify different test chips
• Work closely with Design and DFT teams to develop/verify various functional/DFT tests
• Write functional cover groups and cover points for coverage closure. Perform RTL code coverage, System Verilog Assertion coverage, System Verilog functional coverage
• Drive and adopt new verification methodologies and flows for efficiency improvements.

 

■Qualification

• BCH and above in EE, CS related fields with 3-15 years of hands-on experience
• Strong problem solving, debugging and programming skills (Python/TCL/C++)
• Strong hands-on experience with architecting and developing IP/SoC level reusable verification environments using SystemVerilog UVM methodologies.
• Hands-on experience developing testbench and testcases in System Verilog
• Knowledge in Constrained Random and Coverage Driven testbench  
• Gate Level Simulation experience
• Proficiency in English is a must"