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公司名稱
台灣積體電路製造股份有限公司
工作地點
台灣
專業領域
IC 設計技術
職別
工程師/管理師
職務類型
正職
職務張貼日
2026/03/17
台積公司成立於1987年，率先開創了專業積體電路製造服務之商業模式，自此成為世界領先的專業積體電路製造服務公司。台積公司以領先業界的製程技術及設計解決方案組合支援其客戶及夥伴生態系統的蓬勃發展，以此釋放全球半導體產業的創新。台積公司為534 個客戶提供服務，生產12,682 種不同產品，被廣泛地運用在各種終端市場，例如高效能運算、智慧型手機、物聯網、車用電子與消費性電子產品等。 進一步資訊請至台積公司網站https://www.tsmc.com.tw查詢。
In R&D, Design and Technology Platform (DTP) provides differentiated and world-leading design solutions to enable the implementation of System on Chip (SoC) for leading AI/HPC, communication, automotive and IoT applications on TSMC's diverse silicon and packaging technology platform. We work with the world's leading SoC design teams and ecosystem experts to promote industry-leading process design kits (PDKs) and reusable design blocks for the semiconductor intellectual property core (IP), including standard cell libraries, embedded memory, general-purpose input/output (GPIO), simulation and interface IP, as well as electronic design automation (EDA) tools and design flows for monolithic SoCs and heterogeneous 3DICs. This allows us to accelerate the process of transforming innovation into silicon chips and creating revolutionary changes in daily life!
職務說明
Introduction to our division, System and Chip Design Solutions Development Division.
 
We are digital implementation team inside TSMC. Our mission is to integrate latest process technology with most updated commercial design content (CPU, GPU, DSP, etc.) to demonstrate expected performance, power, and area (PPA) improvement. Our results and developed flows are references for worldwide 1st tier design houses.

Job scope covered by our division:

1. Technology related benchmark & design methodology development.

To understand PPA of TSMC’s new technology and explore possible applications, benchmark activities are conducted. And upon results, technology refinement opportunity to achieve “Design-Technology Co-Design” (DTCO) concept would be explored and tested. Through these benchmark activities, we are also in charge of developing design methodology needed for new process technology.

2. System design & yield learning.

Our division has the only system design team in TSMC. System-level architectures of all test chips in TSMC are developed and defined by our division. Additionally, we have dedicated team for “design-for-test” and “design-for-diagnosis” methodology. This is to ensure defects of test chips can be well detected, located, and analyzed. Related results are critical for yield learning and enhancement for TSMC.

3. Test chip implementation & flow issue solving.

To have design flow (from RTL to GDS) for latest technology truly verified and pipe-cleaned based on product-like design content and spec., real test chip implementation is needed for TSMC. This is also critical for yield learning and improvement. Implementation of such test chip is one of division’s major charter. Comparing to other test chip implementation teams in TSMC, test chips owned by us is most “product-like”. This is to trigger issues that are design and spec. dependent. During implementation stages, we need to analyze and solve these issues so that when customers are using related technology, solutions are well prepared.

4. Support to 1st-tier customers for adopting TSMC’s advanced technology.

When customers are adopting TSMS’s new technologies, they would encounter technical issues not experienced before. Support from TSMC is highly expected to ensure on-schedule project execution. In TSMC, our division is the only team that have experience on integrating latest technology and product-level design content. Thus, we are responsible for providing such services in forms of technical consultant, on-site case debugging, or utility development.

Organization of our division & recruiting departments:

1. Our division, SCDSD, is under Design and Technology Platform (DTP). SCDSD currently have ~150 members distributed in offices at Hsinchu (Taiwan), San Jose (U. S.), and Nanjing (China). Yokohama office is now under planning. Our division work like a mini design house covering all design stages from systemlevel definition to GDS tape-out. Thus, all design stages for digital implementation are covered. (ex: system design, RTL coding, synthesis, DFT, MBIST, verification, PG network design, floorplan, place, CTS, route, timing analysis, power analysis, physical verification, CAD support, etc.)

2.For this job position, we are recruiting talents for below three departments on Hsinchu site. Below are brief introductions to job scopes of these three departments.

Test Chip Development Department:

1. FE implementation and related flow development, covering stages of system-level design, RTL coding, verification, DFT, MBIST, and synthesis.
2. Architecture & methodology development for “design-for-test (DFT)” and “design-for-diagnosis”, focusing on yield learning purpose.
3. Architecture & methodology development for silicon correlation.

Test Chip Physical Design Department:

1. BE implementation and related flow development, covering stages of chip-level planning, PG network design, floorplan, place, CTS, route, power analysis (PDNA sign-off), and physical verification.
2. Design methodology and related CAD utility development for BE implementation, especially for solving issues triggered by new technology. Additionally, we also develop utilities for customer support purpose.
3. Technology benchmark to understand PPA of new technologies.

Chip Implementation CAD:

1. Flow development for RC extraction, timing analysis, and timing fixing
2. CAD platform development for design stage integration, design kits management, and design DB management
3. CAD/EDA development in general for solving all kinds of design issues
職務要求
Expected expertise or technical skills expected:
 
1. Digital implementation concept in general. Familiar w/i. at least one of below design stages for digital implementation.
2. System design, RTL coding, synthesis, DFT, MBIST, verification, PG network design, floorplan, place, CTS, route, timing analysis, power analysis, and physical verification.
3. Linux operation capability.

Scripting and/or programming skill:

1. Knowledge to EDArelated algorithm is nice to have but not necessary.


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營造一個合乎台積公司核心價值與經營理念的全球共融職場，對於公司未來成功至關重要。台積公司對全球共融職場的承諾，旨在讓每位員工無論性別、年齡、身心障礙、宗教、種族、族群、國籍、政治立場或性傾向，都能將其自身的觀點與經驗帶入工作，促進企業推升獲利、增加生產力並釋放創新。我們致力於創建一個公平無障礙的工作場所。台積公司承諾促進文化共融，讓每一位員工都覺得被重視且有能力為企業使命提供貢獻，並為全球各戶提供卓越服務。