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公司名稱
台灣積體電路製造股份有限公司
工作地點
台灣
專業領域
身心障礙應徵者專區
職別
工程師/管理師
職務類型
正職
職務張貼日
2026/03/17
台積公司成立於1987年，率先開創了專業積體電路製造服務之商業模式，自此成為世界領先的專業積體電路製造服務公司。台積公司以領先業界的製程技術及設計解決方案組合支援其客戶及夥伴生態系統的蓬勃發展，以此釋放全球半導體產業的創新。台積公司為534 個客戶提供服務，生產12,682 種不同產品，被廣泛地運用在各種終端市場，例如高效能運算、智慧型手機、物聯網、車用電子與消費性電子產品等。 進一步資訊請至台積公司網站https://www.tsmc.com.tw查詢。
Taiwan Semiconductor Manufacturing Company (TSMC) is dedicated to fostering a friendly and inclusive work environment while actively safeguarding the employment rights of individuals with accessabilities. In compliance with the "People with Disabilities Rights Protection Act," we have specially designed a dedicated talent portal for individuals with accessabilities. We sincerely welcome candidates holding valid disability identification to join TSMC and work with us to shape the future of technology!
職務說明
At the beginning of new module research, IC design engineers and R&D engineers would closely cooperate with customers.

Once the new module technologies are developed, we could accomplish the goal of massive production and have customers’ new product launch in a short time. At TSMC, you will have the opportunity to work with the most advanced module technologies, provide solutions to partners in the global IC design ecosystem, and ensure competitiveness in power, performance, and area.

1. Physical Designer

The principal responsibility of the candidate is to perform complete netlist to GDS physical design steps which include floor plan, PNR, timing closure, IR/EM analysis, layout verification, formal verification, and other tape out related tasks. The candidate will work in a talented team to design advanced chips using cutting-edge process nodes while meeting high standard design requirements.

2. Standard Cell Engineer

(1) Pathfinding of library characterization for leading edge tech nodes.
(2) Support industrial standard library kits generation and QC.
(3) In-house library generation flow and/or utility development.
(4) RC parasitic extraction analysis and APR related analysis.

3. Layout Engineer

(1) IC layout for advanced technology (Std. cell/Memory/AMS/IO).
(2) Layout structure development for new technology.
(3) Pathfinding for new technology development.
(4) Customer engagement and layout support.
(5) Design and technology co-optimization (DTCO).
(6) AI and automation for layout and physical design.

4. System and Chip Design Solutions Development


5. FE design & DFT

(1) Test chips development for advanced nodes, including physical design (APR), logic synthesis and DFT (Scan insertion + ATPG).
(2) Design flow development for test chips design, which requires the programming skills, Tcl, Python, C-shell scripting etc.
(3) Technology benchmarking for PPA evaluation of the advanced nodes.
(4) DTCO (Design & Technology Co-Optimization) pathfinding and development.

6. SRAM Engineer

(1) SRAM design in advanced nodes for mobile, high-performance computing, IoT, automotive applications.
(2) RRAM/MRAM, emerging memory development.
(3) In memory computing research and development.

7. Design Flow/Methodology

(1) Advanced technology process design kits (PDK) and tech files (DRC, LVS, RC, etc.) development and technical support.
(2) Advanced technology design development flow development and technical support.
(3) Automation program development to support design kits and flow development productivity/quality.
職務要求
1. Master's degree in Electrical Engineering or Computer Engineering.
2. Strong proficiency in speaking and writing English.
3. Thorough understanding of place and route flow.
4. Excellent interpersonal and communication skills.
5. Self-motivated and possess excellent team spirit.
6. A valid disability identification issued in Taiwan is required.


#LI-DNI
營造一個合乎台積公司核心價值與經營理念的全球共融職場，對於公司未來成功至關重要。台積公司對全球共融職場的承諾，旨在讓每位員工無論性別、年齡、身心障礙、宗教、種族、族群、國籍、政治立場或性傾向，都能將其自身的觀點與經驗帶入工作，促進企業推升獲利、增加生產力並釋放創新。我們致力於創建一個公平無障礙的工作場所。台積公司承諾促進文化共融，讓每一位員工都覺得被重視且有能力為企業使命提供貢獻，並為全球各戶提供卓越服務。