公司名稱

台灣積體電路製造股份有限公司

工作地點

台灣

專業領域

IC 設計技術

職別

主管職

職務類型

正職

職務張貼日

2026/03/18

台積公司成立於1987年，率先開創了專業積體電路製造服務之商業模式，自此成為世界領先的專業積體電路製造服務公司。台積公司以領先業界的製程技術及設計解決方案組合支援其客戶及夥伴生態系統的蓬勃發展，以此釋放全球半導體產業的創新。台積公司為534 個客戶提供服務，生產12,682 種不同產品，被廣泛地運用在各種終端市場，例如高效能運算、智慧型手機、物聯網、車用電子與消費性電子產品等。 進一步資訊請至台積公司網站https://www.tsmc.com.tw查詢。

As chip sizes increase and packaging technologies become more complex, substrate engineering is emerging as a critical domain. This role supports TSMC’s leadership in 3DIC and advanced packaging by extending expertise beyond chip-level design into packaging-level integration. The team is addressing challenges such as warpage, power delivery, thermal management, and material innovation. Future evolution includes Chip-on-Wafer-on-PCB (CoWoP) under TSMC’s System Technology Optimization program.

The position requires strong design and technology expertise to define future customer requirements, focusing on integrated packaging, dielectric parameters, high-speed I/O, and trade-offs that directly impact system performance. This role is critical in shaping the direction of 3DIC development.

We are seeking a highly skilled and motivated Substrate / Advanced Package Manager to join our cutting-edge 3DIC design team. The ideal candidate will have a strong foundation in semiconductor physics, mechanical engineering principles, and EDA (Electronic Design Automation) tools, with a passion for innovation in advanced packaging design. The role involves design, simulation, and modeling of complex substrate and packaging technologies to support next generation 3DIC applications.

職務說明

1. Design, simulate, and optimize advanced packaging for 3DIC applications.

2. Collaborate with cross-functional teams to define specifications and requirements.

3. Perform modeling of warpage, stress, reliability, and thermal performance using industry-standard EDA tools.

4. Formulate and solve problems in research-driven, often ambiguous domains.

5. Provide guidance on high-speed I/O modeling and integration.

6. Develop and maintain documentation, including specifications, test plans, and design reviews.

7. Stay current with industry trends, tools, and technologies in advanced packaging.

職務要求

Minimum Qualifications

1. Master’s or Ph.D. degree in Electrical Engineering, Mechanical Engineering, or a related field.

2. 15+ years of hands-on expertise in advanced packaging technologies and substrate design.

3. Understanding of semiconductor device physics and packaging process technologies.

4. Strong knowledge of warpage, stress, and thermal effects in packaging.

5. Proven ability to drive solutions in ambiguous, research-oriented contexts.

6. Excellent problem-solving, analytical, and communication skills.

7. Strong collaboration skills, with the ability to mentor junior engineers.

8. Ability to balance strategic insight with hands-on technical execution.

Preferred Qualifications

1. Experience with reliability, IR/EM, and multi-physics analysis.

2. Familiarity with machine learning techniques for design optimization.

3. Patents, publications, or demonstrated innovation in substrate or packaging domains.

Success Metrics

1. Ability to provide impactful, data-driven suggestions that influence design direction.

2. Effective use of modeling and simulation to validate proposals.

3. Establishing trust and credibility with global teams.

4. Enabling adoption of new technologies within the 3DIC ecosystem.

營造一個合乎台積公司核心價值與經營理念的全球共融職場，對於公司未來成功至關重要。台積公司對全球共融職場的承諾，旨在讓每位員工無論性別、年齡、身心障礙、宗教、種族、族群、國籍、政治立場或性傾向，都能將其自身的觀點與經驗帶入工作，促進企業推升獲利、增加生產力並釋放創新。我們致力於創建一個公平無障礙的工作場所。台積公司承諾促進文化共融，讓每一位員工都覺得被重視且有能力為企業使命提供貢獻，並為全球各戶提供卓越服務。