Job Description:
-Chip/Block level floorplan,
-Clock tree synthesis,
-Place & Route,
-RC extraction,
-STA, timing closure,
-IR/EM analysis and fix,
-DRC/LVS/ERC analysis and fix,
-Tape-out sign off.
-APR Flow development
Qualifications:
-BCH degree and above in EE/CS.
-Experienced in digital design/design flow/APR chip implementation related field.
-Experienced in advanced process nodes (28nm and below)
-Familiar with Script languages (shell, python, TCL) or C/C++
-Familiar with APR tools (such as Cadence Innovus and Synopsys IC Compiler II ) & PPA analysis/boost methodology.
-Good customer-oriented attitude and communication skills.
-Good command of Japanese.
-Highly welcome candidates who have less experience but have good related design experience, working attitude and are self-motivated.
-English is a plus.
- 誠信正直: 說真話、不誇張、不作秀。一旦答應,必定不計代價,全力以赴。
- 承諾: 同仁全心全意投入公司,抱著「公司成功、我也成功」的心情,熱忱認真地工作,並且做出最大貢獻。因為承諾是雙向的,公司也會為照顧員工權益全力以赴。
- 創新:創新是公司成長的泉源,不僅僅是有新的想法,還要執行力,做出改變。
- 客戶信任: 我們努力與客戶建立深遠的夥伴關係,並成為客戶信賴且賴以成功的長期重要夥伴。