会社

台湾積体電路製造股份有限公司

会社所在地

台湾

職種

ICデザイン技術

職種

エンジニア／管理者

雇用形態

正社員

投稿日

2026/03/17

Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of over 17 million 12-inch equivalent wafers in 2025. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.

In R&D, Design and Technology Platform (DTP) provides differentiated and world-leading design solutions to enable the implementation of System on Chip (SoC) for leading AI/HPC, communication, automotive and IoT applications on TSMC's diverse silicon and packaging technology platform. We work with the world's leading SoC design teams and ecosystem experts to promote industry-leading process design kits (PDKs) and reusable design blocks for the semiconductor intellectual property core (IP), including standard cell libraries, embedded memory, general-purpose input/output (GPIO), simulation and interface IP, as well as electronic design automation (EDA) tools and design flows for monolithic SoCs and heterogeneous 3DICs. This allows us to accelerate the process of transforming innovation into silicon chips and creating revolutionary changes in daily life!

職務内容

Job content:

 

1. Hands on SOC chip/ block implementation from gate level netlist to GDS tape-out.

2. Develop IC design methodology.

3. Chip tape-out; Design methodology development.

職務資格

Requirement:

 

1. Experience in tape-out with multi-million gates count SOC design. 16nm/10nm/7nm design experience is a plus.

2. Solid skillsets of Cadence/Synsopsys/Mentor EDA tools.

3. Capable of executing timing budgeting, synthesis, P&R, CTS, timing closure, DFT, physical verification, DFM and spice simulations.

4. Experience in CAD methodology and problem solving skill.

5. Familiar with Verilog, Perl/Tcl and C/C++.

6. Good communication in English.

7. Master Degree or above.

#LI-DNI

TSMC 価値観

TSMCは、私たちのビジョンと価値観に共感していただき、会社の持続的な成功に貢献していただける仲間を募集しています。私たちのコアバリューは、企業文化を形成する礎であり、すべての決断や行動の指針であります。以下のプリンシプルに心が響き、業務に体現していただける応募者を心よりお待ちしています。 

• 誠実さ： 私たちは事実のみを語り、誇張や虚飾はしません。私たちは軽率に約束することはありません。一度約束したら、全力を尽くして守ります。
• コミットメント：コミットメントは社員と会社の間に存在する双方向性です。社員は会社に対してロイヤリティを持ち、会社の成功は自分の成功であると心構え、勤勉に働いてベストを尽くします。一方で、会社は社員の利益を最大限に考慮するよう尽力します。 
• イノベーション： イノベーションは会社成長の源泉です。新しいアイデアを発想することに留まらず、そのアイデアを実践するこそがイノベーションです。 
• お客様の信頼：私たちは、お客様と深く永続的なパートナーシップを築くことに尽力します。長期にわたり、お客様の成功を支える、頼れるパートナーであり続けます。

 (TSMCのコアバリューに関する詳細は、こちらをご参照ください：https://www.tsmc.com/japanese/aboutTSMC/values)

Fostering a global inclusive workplace reflects TSMC’s core values and business philosophy and is essential for our future success. Our commitment to global inclusive workplace allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. We strive to create a workplace that is equitable and accessible to all employees. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.