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会社
TSMC Europe B.V
会社所在地
ドイツ-ミュンヘン
職種
研究開発
職種
エンジニア／管理者
雇用形態
正社員
投稿日
2026/07/16
Taiwan Semiconductor Manufacturing Company Ltd. (“TSMC”) is the world’s leading semiconductor foundry. Headquartered in Taiwan, the Company has operation facilities worldwide and the largest logic chip manufacturing capacity in global semiconductor industry. The Company employs a global workforce of over 89.000 and recorded revenue over US$122 billion in 2025. TSMC produces the chips that are found in smart phones, tablets, computers, smart TVs, cars, laptops, games consoles, data centers and many more applications. TSMC sells to a wide variety of customers, including most leading semiconductor companies.
At the TSMC EU Design Center, you’ll work in an exceptional technology and design team to refine your technical and leadership skills within the world's most advanced design service ecosystem. You'll be contributing to the forefront of semiconductor technology, including cutting-edge nonvolatile memory solutions like MRAM and RRAM. Your main focus will be to assist our leading customers in delivering state-of-the-art products that have a transformative impact on people's lives.
職務内容
IP Design Flow & Methodology Development:

1. Design, build, and support unified front-to-back design flows for mixed-signal IP development, bridging analog schematic/layout environments with digital implementation environments
2. Define and enforce best practices for IP reuse, modularity, and multi-process node portability

Mixed-Signal Verification & Modeling:

1. Establish robust Analog/Mixed-Signal (AMS) verification methodologies to enable automated, top-level co-simulations
2. Standardize and automate the generation of high-quality behavioral models to enable early system-level simulations for IP consumers

Interface Timing & Sign-Off:

1. Define methodologies for timing closure across analog-digital IP interfaces, including Static Timing Analysis (STA) on mixed-signal boundaries and constraint generation
2. Build and automate physical verification sign-off flows (DRC/LVS/PEX, EM/IR drop, and reliability analysis) tailored for IP integration

CAD Automation & Scripting:

1. Develop and maintain robust automation scripts (Python, Tcl, SKILL, Perl) to minimize human error, automate repetitive design tasks, and accelerate regression testing

IP Packaging & Release Management:

1. Define standard IP delivery packages (including Liberty files/lib, LEF/GDS, CDL, behavioral models, and integration guidelines)
2. Manage design data, workspaces, and IP version control utilizing configuration management systems
職務資格
  • Education: Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience: 10+ years of experience in CAD, design methodology, or IP development (analog, digital, or mixed-signal).
  • Mixed-Signal Flow Expertise: Strong hands-on experience with industry-standard EDA environments.
  • Analog/Custom: Cadence Virtuoso (ADE, Spectre), Synopsys Custom Compiler.
  • Digital Front/Back-End: Synopsys Design Compiler/PrimeTime, Cadence Genus/Innovus.
  • Mixed-Signal Verification: Cadence Xcelium/AMS Designer, Synopsys VCS/XA.
  • Scripting Skills: Proficiency in scripting languages used in modern EDA flows (Tcl, Python, SKILL, Shell scripting).
  • IP-Specific Knowledge: Deep understanding of IP packaging, process design kits (PDKs), physical extraction (PEX/EM/IR), and boundary timing constraints.
TSMC 価値観
TSMCは、私たちのビジョンと価値観に共感していただき、会社の持続的な成功に貢献していただける仲間を募集しています。私たちのコアバリューは、企業文化を形成する礎であり、すべての決断や行動の指針であります。以下のプリンシプルに心が響き、業務に体現していただける応募者を心よりお待ちしています。 
  • 誠実さ： 私たちは事実のみを語り、誇張や虚飾はしません。私たちは軽率に約束することはありません。一度約束したら、全力を尽くして守ります。
  • コミットメント：コミットメントは社員と会社の間に存在する双方向性です。社員は会社に対してロイヤリティを持ち、会社の成功は自分の成功であると心構え、勤勉に働いてベストを尽くします。一方で、会社は社員の利益を最大限に考慮するよう尽力します。 
  • イノベーション： イノベーションは会社成長の源泉です。新しいアイデアを発想することに留まらず、そのアイデアを実践するこそがイノベーションです。 
  • お客様の信頼：私たちは、お客様と深く永続的なパートナーシップを築くことに尽力します。長期にわたり、お客様の成功を支える、頼れるパートナーであり続けます。
 (TSMCのコアバリューに関する詳細は、こちらをご参照ください：https://www.tsmc.com/japanese/aboutTSMC/values)
It is the policy of TSMC EU to provide equal employment opportunity (EEO) to all persons regardless of age, color, ethnic and national origin, citizenship status, physical or mental disability, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, genetic information, marital status, status with regard to public assistance, veteran status, or any other characteristic protected by federal, state or local law.