Responsibilities:

• High speed interface design (TX/RX, equalization, clocking) for traditional SerDes or chiplet interconnects.
• Evaluate and drive implementation of technology features for high-speed interface, including electrical performance optimization and reliability enhancement.
• 2.5D/3DIC channel modeling.

Requirements:

• Education: Masters or PhD in Electrical Engineering (or similar)
• Must be fluent in English communication, both written and oral
• Must have more than 3 years of relevant industry experience in high-speed interface designs (larger or equal to 10Gbps).
• Understanding of high-speed interface architecture from theory, circuit design to silicon validation.
• Familiarity with EM extraction is preferred.