Job Description
1. RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
2. Design flow/methodology development and innovation for front-end design challenges.
3. Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.
■Qualification
1. BCH and above in EE, CS related fields.
2. 3-10 years working experience. Especially, experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification.
3. Familiar with EDA CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
4. Familiar with tcl/Perl/Python/C++ program.
5. PPA improvement experience is a plus.
6. Familiar with CPU architecture is a plus.
7. Good command of Japanese. Fluent in English is a plus."
- Integrity: Tell the truth. We do not brag. We do not make commitments lightly. Once we make a commitment, we devote ourselves completely to meeting that commitment.
- Commitment: Employees are dedicated to the company, view the company’s success as their own and work diligently to make their best contributions. As commitment is mutual, the Company strives to serve the best interests of its employees.
- Innovation: Innovation is the wellspring of the Company's growth. It means more than new ideas; it means putting ideas into practice.
- Customer Trust: We strive to build deep and enduring relationships with our customers, who trust and rely on us to be part of their success over the long term.