Job Description:
-Chip/Block level floorplan,
-Clock tree synthesis,
-Place & Route,
-RC extraction,
-STA, timing closure,
-IR/EM analysis and fix,
-DRC/LVS/ERC analysis and fix,
-Tape-out sign off.
-APR Flow development
Qualifications:
-BCH degree and above in EE/CS.
-Experienced in digital design/design flow/APR chip implementation related field.
-Experienced in advanced process nodes (28nm and below)
-Familiar with Script languages (shell, python, TCL) or C/C++
-Familiar with APR tools (such as Cadence Innovus and Synopsys IC Compiler II ) & PPA analysis/boost methodology.
-Good customer-oriented attitude and communication skills.
-Good command of Japanese.
-Highly welcome candidates who have less experience but have good related design experience, working attitude and are self-motivated.
-English is a plus.
- Integrity: Tell the truth. We do not brag. We do not make commitments lightly. Once we make a commitment, we devote ourselves completely to meeting that commitment.
- Commitment: Employees are dedicated to the company, view the company’s success as their own and work diligently to make their best contributions. As commitment is mutual, the Company strives to serve the best interests of its employees.
- Innovation: Innovation is the wellspring of the Company's growth. It means more than new ideas; it means putting ideas into practice.
- Customer Trust: We strive to build deep and enduring relationships with our customers, who trust and rely on us to be part of their success over the long term.