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Company
Taiwan Semiconductor Manufacturing Company Limited
Location
Taiwan
Career Area
R&D
Job Type
Manager / Executive
Employment Type
Regular
Posted
May 05, 2025
Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.
Job Responsibilities
1. Lead the design of memory macros and test chips.
2. Collaborate closely with technologists and customers to define PPA specifications, architecture, and design of memory circuits.
3. Demonstrate hands-on expertise in designing memory circuit blocks and utilizing EDA tools for timing, power, signal integrity, EM/IR analysis, static timing, and noise analysis.
4. Drive design verification and implement quality assurance methodologies for memory IP.
5. Define silicon test plans and provide support for post-silicon bring-up and debugging in collaboration with test teams.
6. Manage design projects by planning and organizing design resources, while addressing customer/client requests and events as they arise.
7. Work closely with cross-functional teams across global locations to ensure successful project execution.
Job Qualifications
1. Master’s or Ph.D. degree in Electrical Engineering.
2. Minimum of 8 years of relevant experience in designing memory blocks, including memory macros, voltage/current sense amplifiers, area-efficient address decoders, wordline drivers, control circuits, low-power voltage regulators, charge pump circuits, and memory I/O.
3. Strong understanding of advanced memory technologies, architectures, and specifications to make informed decisions for optimal performance/ power/ area trade-offs in memory systems.
4. Proficiency in using industry-standard EDA tools.
5. Familiarity with DFT circuits is a plus.
6. Previous leadership experience is preferred.
7. Strong interpersonal skills, with the ability and enthusiasm to work collaboratively as part of a team, are highly valued.